1. Field of the Invention
The present invention relates generally to a semiconductor device and a method of fabricating the same. More particularly, the invention relates to a stacked semiconductor device and a method of fabricating the same.
A claim of priority is made to Korean Patent Application 2005-18781, filed on Mar. 7, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Semiconductor apparatuses commonly employ metal-oxide semiconductor (MOS) transistors as switching devices. To provide the highest possible performance, the MOS transistors are generally formed in dense arrays. A somewhat recent innovation used to increase the density of these arrays and also to decrease the leakage current of the transistors is to stack the transistors on top of each other, i.e., to form “stacked transistors.”
For example, FIG. 1 is a circuit diagram of a conventional inverter which may be formed by stacking one transistor on top of another.
Referring to FIG. 1, the inverter comprises first and second transistors TR1 and TR2, both having gate electrodes connected to an input line Vin. First transistor TR1 has a drain connected to an output line Vout and a source connected to ground and second transistor TR2 has a drain connected to a power source providing a power source voltage Vdd and a source connected to output line Vout. As shown in FIG. 1, first transistor TR1 is an NMOS transistor and second transistor TR2 is a PMOS transistor.
Such an inverter device may be constructed by forming the first and second transistors on the same substrate plane. However, stacking the transistors is will increase the density of the transistors.
One common method for forming stacked transistors comprises forming a first transistor on a semiconductor substrate, then forming an interlevel insulation film covering the first transistor, and then forming a second transistor on the interlevel insulation film. The second transistor is formed by creating a body pattern on the interlevel insulation film so that source and drain regions can be formed in the body pattern and then forming a gate electrode on the body pattern.
The above method can be used to fabricate the conventional inverter shown in FIG. 1 by stacking second transistor TR2 on first transistor TR1. However, in order to complete the inverter, a contact must be formed in the interlevel insulation film to connect the drain first transistor TR1 with the source of second transistor TR2. However, because the body pattern is typically very thin, it is difficult to form a good contact connecting first and second transistors TR1 and TR2. For instance, if silicide is used to connect the body pattern to a contact plug, electrical resistance between the body pattern and the silicide may be very high if the connection is not very good. As a result, the connection between the upper and lower transistors may be unstable.